Electronic System Level Design Tool VisualSim

Success Story: Internationally Processor Manufacturer VisualSim was used by the processor architects for the mobile and desktop  processor division. The primary project involved the design of the control  plane in the Processor. The control plane is a Network-on-chip topology that  handles the power requirements, power management and the control  operations of the processor. The manufacture constructed the model of the  Infinity NoC and integrated all the different masters and Slaves. They then  ran simulations for different workloads and use-cases. The purpose was to  identify any bottlenecks, detect corner cases and ensure that the  communication and response met the performance requirements of the  cores.  

There were over 45 masters and slaves in the NoC. Each of them is running at  a different clock rate. The model was built with traffic from different devices  on the Processors sending power requests. There are multiple termination  points on the NoC. 

The control plane is extremely time sensitive, and the entire processor  depends on timing deadline of the requests on the control plane. The analysis  was to evaluate the latency for each request, the buffer usage at each Router,  and throughput on the wires.

The experiments were to evaluate the metrics for different traffic from each  connected device. 

Based on the simulation they selected the Noc topology, connectivity of the  devices, routing plan for each request, Router speed/flit size/buffer size and  the number of power controllers.

The primary advantage of using VisualSim was the immediate availability of  the NoC template model. This could be easily customized for their Infinity  Switch. The second was the availability of traffic models and reports. The goal  was to complete the entire modeling effort in three months and start the  development.

The libraries used from VisualSim were the NoC, traffic, memory, power  library, SystemResources and Queues.